1. Field of the Invention
The present invention relates to a semiconductor device and method for manufacturing thereof.
2. Description of Related Art
A memory cell composing DRAM generally composed of a transistor for the memory cell and a capacitance element. Capacitor over bit line (COB) DRAM having a structure, in which a capacitance element of DRAM is disposed above a bit line, is proposed for achieving higher degree of integration of the memory cell. Typical conventional structure of such COB DRAM is shown in FIG. 18.
In this type of the conventional DRAM, a MOS transistor formed on a semiconductor substrate such as a silicon substrate 10 or the like functions as a transistor for memory cell. A bit line 6 is formed on an upper layer of the transistor for the memory cell via a cell contact interlayer film 8, and a capacitance element 11 is formed on an upper layer of the bit line 6 via a capacitance contact interlayer film 7. The bit line 6 is coupled to a transistor for memory cell formed on the silicon substrate 10 by being coupled through a barrier metal layer 5 to a cell contact 9, and the capacitance element 11 is coupled to the transistor for memory cell formed on the silicon substrate 10 through the capacitance contact 4 and the cell contact 9.
Although FIG. 18 illustrates the barrier metal layer 5 provided as an underlying layer disposed under the bit line 6, it is intended to additionally include the barrier metal layer 5 when the term “bit line 6” appears in the following description.
In such structure, it is designed to include a configuration of maintaining a predetermined spacing between the bit line 6 and the capacitance contact 4 or the cell contact 9, in order to inhibit a generation of electric short circuit. However, the progresses in increasing the level of the integration in the semiconductor devices necessarily reduce the room for the spacing between the bit line 6 and the cell contact 9 or the capacitance contact 4, a short circuit may be occurred between the bit line 6 and the cell contact 9 or the capacitance contact 4 by a misalignment caused in the formation of the bit line 6 or a misalignment caused in the formation of the capacitance contact 4 or the like. When the short circuit is occurred between the bit line 6 and the cell contact 9 or the capacitance contact 4 as described above, failure occurs in the resultant memory cell, thereby reducing the yield of DRAM.
Thus, a semiconductor device additionally including a bit contact interlayer film 13 formed on the cell contact interlayer film 8 is proposed, in order to inhibit the short circuit between the bit line 6 and the cell contact 9. The constitution of such conventional semiconductor device is shown in FIG. 19. In this type of conventional semiconductor device, a bit contact interlayer film 13 is formed after forming the cell contact interlayer film 8, and a bit contact 14 is formed on a portion of the bit contact interlayer film 13 in order to couple the cell contact 9 to the bit line 6. Having such structure, larger room for the spacing for preventing the short circuit between the upper end of the cell contact 9 and the bit line 6 can be acquired. However, sufficient level of inhibition for the short circuit between the bit line 6 and the capacitance contact 4 can not be obtainable by employing such structure.
A semiconductor device having a configuration for inhibiting the short circuit between the capacitance contact 4 and the bit line 6 includes, as shown in FIG. 20, a self-aligned (or self-alignment) contact structure comprising a side wall 17 formed on a material such as silicon nitride film or the like having an etch selectivity against the capacitance contact interlayer film 4 on the side surface of the bit line 6 is proposed (see, for example, JP-A-2002-231,906 and JP-A-2003-7,854). The self alignment contact structure (hereinafter abbreviated as SAC) is a structure, in which circumferences of the bit line 6 are covered with an insulating film such as nitride film or the like to provide an inhibition to the short circuit between the bit line 6 and the capacitance contact 4.
In the manufacture of the semiconductor device having the SAC structure, contact holes are formed in a self-alignment manner by employing an etch mask pattern having a size that is larger than the actual size of the contact hole, and by employing the side wall 17 of the silicon nitride film as an etch stop, which is provided on the side surface of the bit line 6. Having such configuration, the short circuit between the bit line 6 and the capacitance contact 4 can be inhibited when the capacitance contact 4 is misaligned.
Next, a method for manufacturing a semiconductor device having the SAC structure will be described below in reference to FIG. 21 to FIG. 27.
First of all, as shown in FIG. 21, shallow grooves are formed on a silicon substrate 10, similarly as in the typical manufacturing process for DRAM, and the grooves are filled with an insulating material to form element isolation insulating films 3, so that the memory cell region is sectioned into individual cell regions. Then, an impurity is diffused into the silicon substrate 10 to form source drain regions 2, thereby forming a MOS transistor, which will be transistors for the memory cells.
Next, cobalt silicide layers 12 are formed by silicidating the entire surfaces of the diffusion layers and the gates of respective transistors with cobalt. Thereafter, silicon nitride films 1 are formed on the surface of the silicon substrate 10 including the surface of element isolation insulating films 3 to coat the respective transistors.
Next, cell contact interlayer films 8 are formed by using a material such as silicon oxide film or the like so as to cover the respective transistors for memory cells in the memory cell region. Then, contact holes for coupling the bit line and the capacitance element to the transistors for memory cells in the cell contact interlayer films 8 are formed via a selective etch process. Then, tungsten (W) is deposited on the entire surfaces thereof via a chemical vapor deposition (CVD) until the contact holes are filled therewith. Thereafter, the surfaces of the cell contact interlayer films 8 are planarized via a chemical mechanical polishing (CMP) so as to leave W only in respective contact holes, thereby forming cell contacts 9. A cross sectional view of the semiconductor device after the steps so far is finished is shown in FIG. 21.
Next, as shown in FIG. 22, a bit contact interlayer film 13 comprising silicon oxide is formed to a predetermined thickness on the surfaces of the cell contact interlayer films 8 that include exposed surfaces of the cell contact 9 to coat the surfaces of the cell contacts 9. Then, the bit contact interlayer film 13 is etched so that only the positions directly above the portions electrically coupled to the bit lines 6 are selectively etched among the cell contacts 9 to form contact holes, thereby exposing the upper surface of the cell contacts 9. Then, W is deposited via CVD until the formed contact holes are filled therewith, similarly as in the formation process of the cell contacts 9, and the surfaces thereof are planarized via CMP so as to leave W only in respective contact holes, thereby forming bit contacts 14 for coupling to the bit lines 6. A cross sectional view of the semiconductor device after the steps so far is finished is shown in FIG. 22.
Next, as shown in FIG. 23, titanium nitride (TiN) for forming barrier metal layers 5 and tungsten (W) for forming bit lines 6 are deposited on the surfaces of the bit contact interlayer film 13, and multi-layered films comprising a silicon oxide film and a silicon nitride film are formed thereon as hard mask films 15. Then, the hard mask films 15, bit lines 6 and barrier metal layers 5 are patterned to form a bit-line pattern by employing a photo resist (not shown.) A cross sectional view of the semiconductor device after the steps so far is finished is shown in FIG. 23.
Next, as shown in FIG. 24, s silicon nitride film 16 is grown to a predetermined thickness on the entire surfaces to cover the hard mask films 15 and the bit lines 6.
Next, as shown in FIG. 25, the silicon nitride film 16 is etched back by conducting an anisotropic etch process so as to leave the silicon nitride film only on the side. surfaces of the bit lines 6 and the barrier metal layers 5, thereby forming side walls 17.
Next, as shown in FIG. 26, silicon oxide films are formed to cover the bit lines 6, thereby forming capacitance contact interlayer films 7. Then, the capacitance contact interlayer films 7 are etched so that only the positions directly above the portions electrically coupled to capacitance elements 11 are selectively etched among the cell contacts 9 to form contact holes.
In this configuration, even if misalignments of the contact holes occur in the formation process thereof to cause the contact holes overlapping with the bit lines 6, unwanted etch of the side walls 17 is avoided, because the side walls 17 formed on the side surfaces of the bit lines 6 comprise the silicon nitride film, the etch ratio of which to the silicon oxide film contained in the capacitance contact interlayer film 7 is much higher. The exposure of the bit lines 6 in the contact hole is also avoided because the formed contact holes are self-aligned.
Then, similarly as in the formation process for the cell contacts 9 or the bit contacts 14, W is deposited via CVD until the contact holes are filled therewith, and the surfaces thereof are planarized via CMP so as to leave W only in respective contact holes, thereby forming capacitance contacts 4 for coupling to the capacitance elements 11. A cross sectional view of the semiconductor device after the steps so far is finished is shown in FIG. 26.
Then, the capacitance element 11 for coupling to the capacitance contact 4 is finally formed to complete the semiconductor device. A cross sectional view of the semiconductor device after the steps so far is finished is shown in FIG. 27.
The microscopic contact holes can be formed without causing a short-circuit to the bit line 6 by employing the SAC structure described above. However, when the SAC structure described above is employed, the manufacturing process additionally requires the process steps such as a step for forming hard mask film 15 on the bit line 6, a step for depositing a nitride film for forming the side wall 17, a step for etching back the side wall 17 or the like, thereby increasing the number of the processing steps in the manufacturing process.
The SAC structure is characterized in that nitride films are disposed on both of the upper part and the side wall part of an interconnect such as bit line 6 or the like, and therefore this configuration provides an advantageous effect of inhibiting the short circuit even if a misalignment occurs during the formation of the contact holes (capacitance contacts) between interconnects or even if a layout of intentionally disposing the contact holes in the region of upper part of the interconnect is employed.
In order to form such SAC structure, it is necessary to employ an etch condition including higher selective etch ratio of the oxide film of the capacitance contact interlayer film 7 to the nitride film existing in the upper part and the side walls of the interconnect such as bit line 6 or the like, when the contact hole for the capacitance contact 4 is processed. In addition, it is also necessary to employ the nitride film having better film quality. Since the deposition process at an elevated temperature is often required for depositing the nitride film having better film quality, the logic transistor having higher performance is often deteriorated. Consequently, when the memory cell regions and other types of circuits are formed on the same semiconductor substrate, such as a combined logic/DRAM device, it is difficult to obtain the nitride film having better film quality.
In addition, the SAC structure employs a hard mask of SiO2/SiN films or SiN film instead of resist mask during the etch process for the interconnects such as the bit lines 5 or the like. This provides a thicker nitride film formed on the upper part of the interconnect, thereby providing higher height of the interconnects such as the bit lines 5 or the like. As such, a higher aspect ratio of a line and space (L/S) portion of the interconnect (bit line) is obtainable in the process for forming the nitride film after etching the interconnects (process for forming the side walls 17 of the interconnects) and in the process for forming the capacitance contact interlayer film 7 after forming the side wall 17, and thus it is difficult to sufficiently achieve the better filling process.
Further, thicker nitride films for forming the side walls 17 are necessary to be formed, in order to leave thicker nitride films on the side wall portions of the interconnect such as the bit line 6 or the like in the SAC structure. However, the progressing miniaturization of the device reduces the size of the L/S portion to cause a conjunction between the interconnects, such that it becomes difficult to form thicker interconnect.
In addition, thicker nitride film formed on the interconnect provide thicker contact interlayer film in the SAC process, and thus it is disadvantageous for the miniaturization. This is due to the difficulties in the ability to etch thereof or in the ability to fill the contacts (with barrier metal, W or the like), rather than the problem of the resistance of the resist. Larger thickness of the contact interlayer film provides higher contact resistance.
Since the conventional method for manufacturing the semiconductor device described above employs the SAC configuration, in which the hard mask film is provided on the upper portion of the interconnect such as bit line and the side wall comprising the nitride film is formed on the side surface thereof, there have been rooms for providing improvements on the following points:
(1) Additional process steps of: depositing a hard mask film on the bit line; depositing a nitride film to form side walls; etching back the side wall, or the like, are required, thereby increasing the number of the steps of the manufacturing process,
(2) Since the material having higher selective etch ratio should be selected by employing the nitride film having better film quality, which requires the deposition process at an elevated temperature, it is difficult to apply the SAC structure to the combined logic/DRAM device comprising the transistor having higher performance, which tends to be deteriorated at an elevated temperature.
(3) Since the hard mask film should be formed on the bit line, the height of the bit line is necessarily higher, and the progressing miniaturization causes difficulties in the process for filling the spaces between bit lines with interlayer films or in the process for composing the nitride films on the side walls of the bit lines.